Dual panel pixel readout in an imager
US7652703B2 · kind B2 · utility
7Cited by
10References
22Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 12, 2004 |
| Grant date | Jan 26, 2010 |
| Priority date | — |
| Expiry date | Feb 21, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/78
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An imager having two panels of pixels (i.e., the imager's rows of pixels are split into two panels) that are controllable by separate row decoders. The dual panel architecture allows pipelining of pixel readout and column readout operations to improve the imager's frame rate. The dual panel architecture may use a standard pixel configuration, a shared column and/or a shared row and column configuration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.