Method and apparatus for testing a controlled impedance buffer
US7653505B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2008 |
| Grant date | Jan 26, 2010 |
| Priority date | — |
| Expiry date | Jul 30, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31715
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and apparatus is provided to utilize the configurability of a programmable logic device (PLD), so as to reduce the complexity of special test equipment (STE) fixtures that are required to test the PLD. The output drivers of certain I/O buffers of the PLD that are not under test may be configured to exhibit a particular impedance magnitude. The impedance magnitude of the output drivers that are not under test may then be used to supply the reference impedance that is required by the digitally controlled impedance (DCI) controllers of the I/O buffers that are under test. The DCI controllers may then correctly configure the impedance magnitude of the respective I/O buffers under test, so as to test the functionality of the controlled impedance buffers for I/O standards that require controlled impedance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.