Digital logic circuit for adding three binary words and method of implementing same
US7653677B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2005 |
| Grant date | Jan 26, 2010 |
| Priority date | — |
| Expiry date | Jun 7, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/509
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital logic circuit includes at least one stage. Each stage includes sum logic, combinatorial logic, and carry chain logic. The sum logic is configured to generate a first sum signal from a first set of three input signals. The combinatorial logic includes a carry generation portion and a sum generation portion. The carry generation portion is configured to generate a first carry signal from a second set of three input signals. The sum generation portion is configured to generate a second sum signal from the first sum signal and the first carry signal. The carry chain logic is configured to process the first sum signal, the second sum signal, and a carry-in signal to generate a carry-out signal and a third sum signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.