Direct digital synthesis circuit
US7653678B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2006 |
| Grant date | Jan 26, 2010 |
| Priority date | — |
| Expiry date | Jul 10, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06G7/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A direct digital synthesis circuit (108) includes a plurality of current sources (210, 211, 212), an output circuit (200), and a logical multiplier circuit (202). The output circuit (200) provides a synthesized waveform (164) output and includes a first (206) and second branch (208). The logical multiplier circuit (202) is operatively coupled to the plurality of current sources (210, 211, 212) and to the output circuit (200). The logical multiplier circuit (202) is operative to receive a plurality of signals. The logical multiplier circuit is also operative to selectively increase a first current flow through the first branch (206) by a determined magnitude and decrease a second current flow through the second branch (208) by the determined magnitude based on the plurality of signals. The synthesized waveform (164) is based on the first and second currents.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.