Delay fault detection using latch with error sampling
US7653850B2 · kind B2 · utility
6Cited by
5References
10Claims
0Family size
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Key dates
| Filing date | Jun 5, 2007 |
| Grant date | Jan 26, 2010 |
| Priority date | — |
| Expiry date | Apr 7, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments provide sampling of a data signal output from a path stage using a latch, sampling of the data signal output from the path stage using an edge-triggered flip-flop, comparing a first value output by the latch with a second value output by the edge-triggered flip-flop, and generating an error signal if the first value is different from the second value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.