Wafer level package with good CTE performance
US7655501B2 · kind B2 · utility
34Cited by
4References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2008 |
| Grant date | Feb 2, 2010 |
| Priority date | — |
| Expiry date | Jul 18, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a structure of package comprising a substrate with a pre-formed die receiving cavity formed and/or terminal contact metal pads formed within an upper surface of the substrate. A die is disposed within the die receiving cavity by adhesion and a dielectric layer formed on the die and the substrate. At least one re-distribution built up layer (RDL) is formed on the dielectric layer and coupled to the die via contact pad. Connecting structure, for example, UBM is formed over the re-distribution built up layer. Terminal Conductive bumps are coupled to the UBM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.