Method for calibrating semiconductor device tester
US7656178B2 · kind B2 · utility
0Cited by
12References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 6, 2007 |
| Grant date | Feb 2, 2010 |
| Priority date | — |
| Expiry date | Apr 11, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31725
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for calibrating a semiconductor device tester is disclosed. In accordance with method of the present invention, a timing is calibrated using a programmable delay device and calibration boards so as to remove a timing difference between channels and compensate a linearity of the programmable delay device for an adjustment of a timing by building and using a database of the round trip delay actually generated during the test.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.