Distributed memory in field-programmable gate array integrated circuit devices

US7656191B2 · kind B2 · utility

Assignee

• Altera Corporation · US

Inventors

• David Lewis · Toronto, CA
• Paul Leventis · Toronto, CA
• Vaughn Betz · Toronto, CA
• Thomas Yau-Tsun Wong · Markham, CA
• Andy L. Lee · San Jose, US
• Philip Pan · Fremont, US

Key dates

• Filing date: May 30, 2008
• Grant date: Feb 2, 2010
• Expiry date: May 30, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K19/1776
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

Circuitry for facilitating the use of the memory elements in the look-up tables (“LUTs”) of a field programmable gate array (“FPGA”) as user-accessible, distributed RAM. For example, a register associated with a LUT and that is not needed in the read data path in user RAM mode can be used to register data for writing in user RAM mode. As another example, an otherwise unneeded register associated with a LUT can be used to provide a synchronous read address signal for user RAM mode. Several other features are shown for similarly facilitating user RAM mode with minimal (if any) additional circuitry being required in the FPGA.