Method to gate off PLLS in a deep power saving state without separate clock distribution for power management logic
US7656237B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2004 |
| Grant date | Feb 2, 2010 |
| Priority date | — |
| Expiry date | Apr 23, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S331/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus, a method, and a computer program are provided to gate a Phased Locked Loop (PLL). In microprocessors, the clock distribution system can account for a substantial amount of power consumption. Gating the PLLs, however, has been difficult because of the usual requirement for a separate clock for control logic and because the PLL requires timed to reacquire phase/frequency lock. Therefore, lock detection logic can be employed to allow the PLL to reacquire phase/frequency lock. Additionally, signals from external devices and the processor can be employed to gate the PLL and allow the processor to be awakened without a need for a separate clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.