Non-volatile memory cell with improved programming technique with decoupling pass gates and equalize transistors
US7656698B1 · kind B1 · utility
4Cited by
14References
9Claims
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Key dates
| Filing date | Jan 23, 2007 |
| Grant date | Feb 2, 2010 |
| Priority date | — |
| Expiry date | Jan 23, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0441
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A 4-transistor non-volatile memory (NVM) cell includes a static random access memory (SRAM) cell structure. The NVM cell utilizes a reverse Fowler-Nordheim tunneling programming technique that, in combination with the SRAM cell structure, allows an entire array to be programmed at one cycle. Equalize transistors are utilized to obtain more uniform voltage on the floating gates after an erase operation. Utilization of decoupling pas gates during a read operation results in more charge difference on floating gates of programmed and erased cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.