Row active time control circuit and a semiconductor memory device having the same
US7656741B2 · kind B2 · utility
2Cited by
1References
24Claims
0Family size
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Key dates
| Filing date | Jan 10, 2008 |
| Grant date | Feb 2, 2010 |
| Priority date | — |
| Expiry date | Apr 12, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A row active time control circuit is described that includes a master signal generating circuit and a row active control signal generating circuit. The master signal generating circuit generates one or more row active master signals based on an active command signal, a pre-charge command signal, and one or more row active control signals. The row active control signal generating circuit generates a pulse signal that oscillates based on the one or more row active master signals. The row active control signal also generates the one or more row active control signals by dividing a frequency of the generated pulse signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.