Method and system for a digital signal processor debugging during power transitions
US7657791B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2006 |
| Grant date | Feb 2, 2010 |
| Priority date | — |
| Expiry date | Nov 5, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3656
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. A method and system control transferring data between debugging registers and digital signal processor processes in association with a power transition sequence of the digital signal processor. In a digital signal processor, debugging registers associate with the core processor process and the debugging process. Control bits control transferring data among the debugging registers, the core processor process and the debugging process. The control bit prevents transferring data among the debugging registers, the core processor process and the debugging process in the event of a power transition sequence. Control bits also prevent a power transition sequence of the digital signal processor in the event of transferring data among the debugging registers and the core processor process or the debugging process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.