Lucian Codrescu
88Patents
10h-index
54Co-inventors
77Inventor score
Filing activity: Mar 21, 2005 → Sep 22, 2016
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8639913B2 | Multi-mode register file for use in branch prediction | Physics | 37 | Active |
| US7676647B2 | System and method of processing data using scalar/vector instructions | Physics | 28 | Active |
| US8397238B2 | Thread allocation and clock cycle adjustment in an interleaved multi-threaded processor | Physics | 17 | Active |
| US8243100B2 | System and method to perform fast rotation operations | Physics | 14 | Active |
| US8341353B2 | System and method to access a portion of a level two memory and a level one memory | Physics | 14 | Active |
| US8370806B2 | Non-intrusive, thread-selective, debugging method and system for a multi-thread digital signal processor | Physics | 13 | Active |
| US8140823B2 | Multithreaded processor with lock indicator | Emerging Cross-Sectional Technologies | 13 | Active |
| US8756601B2 | Memory coherency acceleration via virtual machine migration | Physics | 12 | Active |
| US8341604B2 | Embedded trace macrocell for enhanced digital signal processor debugging operations | Physics | 11 | Active |
| US7398371B2 | Shared translation look-aside buffer and method | Emerging Cross-Sectional Technologies | 11 | Expired |
| US8145874B2 | System and method of data forwarding within an execution unit | Physics | 10 | Active |
| US8250332B2 | Partitioned replacement for cache memory | Physics | 9 | Active |
| US8190854B2 | System and method of processing data using scalar/vector instructions | Physics | 9 | Active |
| US7917907B2 | Method and system for variable thread allocation and switching in a multithreaded processor | Physics | 8 | Active |
| US8656145B2 | Methods and systems for allocating interrupts in a multithreaded processor | Physics | 8 | Active |
| US7657791B2 | Method and system for a digital signal processor debugging during power transitions | Physics | 8 | Active |
| US9147123B2 | System and method to perform feature detection and to determine a feature score | Physics | 8 | Active |
| US9396012B2 | Systems and methods of using a hypervisor with guest operating systems and virtual processors | Physics | 7 | Active |
| US8380966B2 | Method and system for instruction stuffing operations during non-intrusive digital signal processor debugging | Physics | 5 | Active |
| US7913255B2 | Background thread processing in a multithread digital signal processor | Physics | 5 | Active |
| US7590824B2 | Mixed superscalar and VLIW instruction issuing and processing method and system | Physics | 4 | Expired |
| US7523295B2 | Processor and method of grouping and executing dependent instructions in a packet | Physics | 4 | Expired |
| US8417922B2 | Method and system to combine multiple register units within a microprocessor | Physics | 4 | Active |
| US9122486B2 | Bimodal branch predictor encoded in a branch instruction | Physics | 4 | Active |
| US8972642B2 | Low latency two-level interrupt controller interface to multi-threaded processor | Physics | 4 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.