Method and system for implementing routing refinement and timing convergence
US7657860B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2007 |
| Grant date | Feb 2, 2010 |
| Priority date | — |
| Expiry date | Mar 9, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is an improved method, system, and article of manufacture for implementing routing for an electrical circuit and chip design. A routing architecture can be represented as a spectrum of different granular routing levels. Instead of routing based upon area, routing can be performed for specific routes or portions of routes. Different types of representation or levels of abstraction for the routing can be used for the same net or route. Partial topological reconfiguration, refinement, or rip-up can be performed for a portion of the integrated circuit design, where the portion is smaller than an entire route or net. Non-uniform levels of routing activities or resources may be applied to route the design. Prioritization may be used to route certain portions of the design with greater levels of detail, abstraction, or resources than other portions of the design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.