Safe store for speculative helper threads
US7657880B2 · kind B2 · utility
13Cited by
5References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 1, 2003 |
| Grant date | Feb 2, 2010 |
| Priority date | — |
| Expiry date | May 1, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3851
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The latencies associated with retrieving instruction information for a main thread are decreased through the use of a simultaneous helper thread. The helper thread is permitted to execute Store instructions. Store blocker logic operates to prevent data associated with a Store instruction in a helper thread from being committed to memory. Dependence blocker logic operates to prevent data associated with a Store instruction in a speculative helper thread from being bypassed to a Load instruction in a non-speculative thread.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.