Dual metal gate finFETs with single or dual high-K gate dielectric

US7659157B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Brian J. Greene · Wappingers Falls, US
• Mahender Kumar · Hopewell Junction, US

Key dates

• Filing date: Sep 25, 2007
• Grant date: Feb 9, 2010
• Expiry date: Sep 28, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6211

Abstract

A first high-k gate dielectric layer and a first metal gate layer are formed on first and second semiconductor fins. A first metal gate ring is formed on the first semiconductor fin. In one embodiment, the first high-k gate dielectric layer remains on the second semiconductor fin. A second metal gate layer and a silicon containing layer are deposited and patterned to form gate electrodes. In another embodiment, a second high-k dielectric layer replaces the first high-k dielectric layer over the second semiconductor fin, followed by formation of a second metal gate layer. A first electrode comprising a first gate dielectric and a first metal gate is formed on the first semiconductor fin, while a second electrode comprising a second gate dielectric and a second metal gate is formed on the second semiconductor fin. Absence of high-k gate dielectric materials on a gate wiring prevents increase in parasitic resistance.