Mahender Kumar
24Patents
8h-index
52Co-inventors
74Inventor score
Filing activity: Oct 13, 2003 → Jun 15, 2018
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7118986B2 | STI formation in semiconductor device including SOI and bulk silicon regions | Electricity | 240 | Expired |
| US7151023B1 | Metal gate MOSFET by full semiconductor metal alloy conversion | Electricity | 46 | Expired |
| US7659157B2 | Dual metal gate finFETs with single or dual high-K gate dielectric | Electricity | 23 | Active |
| US8188574B2 | Pedestal guard ring having continuous M1 metal barrier connected to crack stop | Electricity | 17 | Active |
| US7485510B2 | Field effect device including inverted V shaped channel region and method for fabrication thereof | Electricity | 14 | Active |
| US10461186B1 | Methods of forming vertical field effect transistors with self-aligned contacts and the resulting structures | Electricity | 12 | Active |
| US7375410B2 | Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof | Electricity | 11 | Expired |
| US7485537B2 | Method of fabricating a vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness | Electricity | 8 | Active |
| US7115965B2 | Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness for low-substrate bias operation | Electricity | 8 | Expired |
| US7691716B2 | Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness for low-substrate bias operation | Electricity | 7 | Active |
| US10770388B2 | Transistor with recessed cross couple for gate contact over active region integration | Electricity | 6 | Active |
| US7528027B1 | Structure and method for manufacturing device with ultra thin SOI at the tip of a V-shape channel | Electricity | 5 | Active |
| US7763518B2 | Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof | Electricity | 4 | Active |
| US9812324B1 | Methods to control fin tip placement | Electricity | 4 | Active |
| US7911024B2 | Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof | Electricity | 4 | Active |
| US7790553B2 | Methods for forming high performance gates and structures thereof | Electricity | 3 | Active |
| US8053838B2 | Structures, fabrication methods, design structures for strained fin field effect transistors (FinFets) | Electricity | 3 | Active |
| US7790541B2 | Method and structure for forming multiple self-aligned gate stacks for logic devices | Electricity | 2 | Active |
| US7394131B2 | STI formation in semiconductor device including SOI and bulk silicon regions | Electricity | 1 | Active |
| US9780002B1 | Threshold voltage and well implantation method for semiconductor devices | Electricity | 1 | Active |
| US8610217B2 | Self-protected electrostatic discharge field effect transistor (SPESDFET), an integrated circuit incorporating the SPESDFET as an input/output (I/O) pad driver and associated methods of forming the SPESDFET and the integrated circuit | Electricity | 0 | Active |
| US7943474B2 | EDRAM including metal plates | Electricity | 0 | Active |
| US6995094B2 | Method for deep trench etching through a buried insulator layer | Electricity | 0 | Expired |
| US10566328B2 | Integrated circuit products with gate structures positioned above elevated isolation structures | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.