Semiconductor device including a floating gate memory cell with a superlattice channel
US7659539B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2006 |
| Grant date | Feb 9, 2010 |
| Priority date | — |
| Expiry date | Feb 11, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A semiconductor device may include a semiconductor substrate and at least one non-volatile memory cell. The at least one memory cell may include spaced apart source and drain regions, and a superlattice channel including a plurality of stacked groups of layers on the semiconductor substrate between the source and drain regions. Each group of layers of the superlattice channel may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon, which may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A floating gate may be adjacent the superlattice channel, and a control gate may be adjacent the second gate insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.