Patent · US Active

Method and apparatus for testing electronic components within horizontal and vertical boundary lines of a wafer

US7659743B2 · kind B2 · utility

1Cited by

8References

7Claims

0Family size

Assignee

SUSS MicroTec Test Systems GmbH · DE

Inventors

Stojan Kanev · Sacka, DE
Jorg Kiesewetter · Thiendorf, DE

Key dates

Filing date	Nov 29, 2007
Grant date	Feb 9, 2010
Priority date	—
Expiry date	Nov 29, 2027

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/2887
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

A method and an apparatus are provided which make it possible, when testing chips arranged on a wafer, to be able to test optionally both additional components arranged on horizontal boundary lines and on vertical boundary lines. The additional components arranged on horizontal boundary lines are tested in a first position of the wafer. For testing the additional components arranged on vertical boundary lines, the wafer is rotated about its vertical axis through 90° relative to the first position into a second position. The apparatus comprises a housing and, in the housing, at least one test probe for making contact with an electronic component, a chuck for moving the wafer and a rotatably mounted additional plate operatively connected to the chuck.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.