Layout structures and methods of fabricating layout structures
US7660141B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 20, 2007 |
| Grant date | Feb 9, 2010 |
| Priority date | — |
| Expiry date | Sep 9, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/482
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Example embodiments may provide a layout structure and layout method for a memory device that may reduce the area of the memory device. Example embodiment layout structures may include a first region and/or a second region. First and second sensing MOS transistors of a sense amplifier that senses data of a bit line and a complementary bit line may be arranged in the first region. First, second and third equalization MOS transistors of an equalizer that equalizes the bit line and the complementary bit line may be arranged In the second region located apart from the first region, Sensing NMOS transistors and equalization NMOS transistors may share an N-type active region in the layout structure of a memory device, and the area of a sense amplifier may be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.