Low power memory device
US7660183B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 1, 2005 |
| Grant date | Feb 9, 2010 |
| Priority date | — |
| Expiry date | Aug 1, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a memory device having a memory core and a signal interface, receiving a command that specifies at least a portion of a memory access. During the memory access, transferring data between the memory core and the signaling interface, and transferring the data between the signaling interface and an external signal path, and prior to transferring the data between the signaling interface and the external signal path, receiving enable information to selectively enable at least a first memory resource and a second memory resource, wherein each of the first memory resource and the second memory resource performs a control function associated with the memory access.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.