Patent · US Active

System and method for verification of cache snoop logic and coherency between instruction & data caches for processor design verification and validation

US7661023B2 · kind B2 · utility

7Cited by

20References

20Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Sampan Arora · Bengaluru, IN
Shubhodeep Roy Choudhury · Savanuru, IN
Manoj Dusanapudi · Bengaluru, IN
Sunil Suresh Hatti · Gokul, IN
Shakti Kapoor · Austin, US
Chakrapani Rayadurgam · Savanuru, IN

Key dates

Filing date	Jul 18, 2007
Grant date	Feb 9, 2010
Priority date	—
Expiry date	Jul 19, 2028

Classification

Technology area (CPC G)Physics
CPC primaryG06F11/261
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A system and method for verifying cache snoop logic and coherency between instruction cache and data cache using instruction stream “holes” that are created by branch instructions is presented. A test pattern generator includes instructions that load/store data into instruction stream holes. In turn, by executing the test pattern, a processor thread loads an L2 cache line into both instruction cache (icache) and data cache (dcache). The test pattern modifies the data in the dcache in response to a store instruction. In turn, the invention described herein identifies whether snoop logic detects the change and updates the icache's corresponding cache line accordingly.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.