Exception types within a secure processing system
US7661105B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2003 |
| Grant date | Feb 9, 2010 |
| Priority date | — |
| Expiry date | Jan 23, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/481
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for processing data includes a processor operable in a plurality modes including at least one secure mode being a mode in a secure domain and at least one non-secure mode being a mode in a non-secure domain. When the processor is executing a program in a secure mode the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. The processor is responsive to one or more exception conditions for triggering exception processing using an exception handler. The processor is operable to select the exception handler from among a plurality of possible exception handlers in dependence upon whether the processor is operating in the secure domain or the non-secure domain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.