Semiconductor wafer boat for batch processing

US7661544B2 · kind B2 · utility

Assignee

• TOKYO ELECTRON LIMITED · JP

Inventor

• Frank Herzog · Lichtenfels, DE

Key dates

• Filing date: Feb 1, 2007
• Grant date: Feb 16, 2010
• Expiry date: May 20, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/67309
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A boat is provided for stacking semiconductor wafers vertically in processes in which low friction deposits may coat wafer supporting surfaces. In carbon processes, for example, low friction coatings can form that allow the wafers to slip sideways in the boat, leaving them sufficiently out of alignment to cause wafer breakage in handling. Typical boats for these processes having vertical legs, typically three or four in number, in which aligned notches support each of the wafers. The slots provide enough clearance around the edge of the wafer to facilitate loading and unloading of the wafers without wafer damage, as long as the wafers remain centered. For low friction process environments, each notch is provided with a shallow recess on which the edge of a wafer can rest. The recess adds a low step close to the wafer edge that resists horizontal sliding movement of the wafer. Wafers are loaded by inserting them into the boat in a plane spaced above the steps, then lowered onto the recesses.