Strained transistor integration for CMOS
US7662689B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2003 |
| Grant date | Feb 16, 2010 |
| Priority date | — |
| Expiry date | Mar 18, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.