Formation of through-wafer electrical interconnections and other structures using a thin dielectric membrane
US7662710B2 · kind B2 · utility
26Cited by
5References
11Claims
0Family size
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Key dates
| Filing date | Apr 6, 2009 |
| Grant date | Feb 16, 2010 |
| Priority date | — |
| Expiry date | Apr 6, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Providing through-wafer interconnections in a semiconductor wafer includes forming a sacrificial membrane in a pre-existing semiconductor wafer, depositing metallization over one side of the wafer so as to cover exposed portions of the sacrificial membrane facing the one side of the wafer, removing exposed portions of the sacrificial membrane facing the other side of the wafer, and depositing metallization over the other side of the wafer so as to contact the previously deposited metallization. Techniques also are disclosed for providing capacitive and other structures using thin metal membranes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.