Wafer level chip size packaged chip device with a double-layer lead structure and method of fabricating the same
US7663213B2 · kind B2 · utility
17Cited by
3References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2006 |
| Grant date | Feb 16, 2010 |
| Priority date | — |
| Expiry date | May 7, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention disclosed a wafer level chip size packaged chip device with a double-layer lead structure and methods of fabricating the same. The double-layer lead is designed to meet a tendency of increasing quantity per area of peripheral arrayed compatible pads on a semiconductor chip, and also to save more space for layout of lead on the chip bottom surface for avoiding potential short inbetween which happen in increasing probability with increasing quantity per area on the condition of one-layer lead.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.