Logic compatible arrays and operations
US7663916B2 · kind B2 · utility
17Cited by
15References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2007 |
| Grant date | Feb 16, 2010 |
| Priority date | — |
| Expiry date | Mar 5, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An array of memory cells arranged in a plurality of rows and a plurality of columns are provided. The array includes a first program line in a first direction, wherein the first program line is connected to program gates of memory cells in a first row of the array; a first erase line in the first direction, wherein the first erase line is connected to erase gates of the memory cells in the first row of the array; and a first word-line in the first direction, wherein the first word-line is connected to word-line nodes of the memory cells in the first row of the array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.