Delayed sense amplifier multiplexer isolation
US7663955B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 22, 2006 |
| Grant date | Feb 16, 2010 |
| Priority date | — |
| Expiry date | Feb 4, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and circuit arrangements are provided for improving equalization of sense nodes of a sense amplifier in a semiconductor memory device. When a memory array segment on a side a sense amplifier has a bitline leakage anomaly for which the sense amplifier is to be isolated when that memory is in an unselected state, isolation of the sense amplifier from the memory array segment is delayed when transitioning from a selected state of the memory array segment to an unselected state of the memory array segment. The duration of the delay is sufficient to allow time for equalization of the sense nodes of the sense amplifier before isolating the sense amplifier from the memory array segment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.