Pleisiochronous repeater system and components thereof
US7664166B2 · kind B2 · utility
4Cited by
8References
31Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2004 |
| Grant date | Feb 16, 2010 |
| Priority date | — |
| Expiry date | Feb 10, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0091
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A pleisiochronous repeater system and components thereof are disclosed. In one particular exemplary embodiment, a pleisiochronous repeater system component may be realized as a receiver circuit comprising a clock multiplier that multiplies a reference clock signal by an integer multiple to generate a data clock signal. The receiver circuit may also comprise a divider circuit that generates a timing reference signal having a frequency that is not an integer divisor of a frequency of the reference clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.