Apparatus and method for switching clocks while preventing glitches and data loss
US7664212B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 2005 |
| Grant date | Feb 16, 2010 |
| Priority date | — |
| Expiry date | Sep 13, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0688
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A apparatus (700) and method (600) are presented for preventing glitches and data loss in an Digital Base Band (DBB) portion (110) of an Ultra Wideband (UWB) receiver. a first and a second recovered clock (111, 112) and an external clock (109) can be input to a switch (116). Logical rules (490) can be used to determine conditions under which to hold the state of an output clock (310, 320) based on the states of a first clock (410, 420, 430, 440) and a second clock (450, 460, 470, 480) and the state of a switch request signal (312). In addition to holding the state of the output clock, a first data stream (501) associated with the first clock and a second data stream (502) associated with the second clock can be synchronized such that when switching from the first to the second clock no data loss will be experienced in the data stream.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.