Patent · US Active

Memory interface circuitry with phase detection

US7664978B2 · kind B2 · utility

12Cited by

9References

20Claims

0Family size

Assignee

Altera Corporation · US

Inventors

Ali Burney · Fremont, US
Sanjay K. Charagulla · San Jose, US

Key dates

Filing date	Jul 17, 2006
Grant date	Feb 16, 2010
Priority date	—
Expiry date	Feb 6, 2028

Classification

Technology area (CPC G)Physics
CPC primaryG06F1/10
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Integrated circuits such as programmable logic device integrated circuits with memory interface circuitry are provided. The memory interface circuitry measures the timing characteristics of an associated memory during a series of dummy read operations. A multiplexer and phase detector are used to measure phase shifts of memory group clock signals compared to a system clock signal. The memory interface circuitry uses these measurements to adjust a delay-locked-loop circuit. The delay-locked-loop circuit produces a capture clock that is used to read data from the memory.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.