Method and system for debugging using replicated logic and trigger logic
US7665046B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2007 |
| Grant date | Feb 16, 2010 |
| Priority date | — |
| Expiry date | Jul 25, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and system for debugging using replicated logic and trigger logic is described. A representation of a circuit is compiled. One or more signals are selected for triggering and trigger logic is inserted into the circuit. A portion of the circuit is selected for replication. The selected portion of the circuit is replicated and delay logic is inserted to delay the inputs into the replicated portion of the circuit. The representation of the circuit is recompiled and programmed into a hardware device. A debugger may then be invoked. One or more of the triggering signals are selected. For each selected triggering signal, one or more states are selected to setup a trigger condition. The hardware device may then be run. The replicated portion of the circuit will be paused when the trigger condition occurs. The states of registers in the replicated portion of the circuit and the sequence of steps that led to the trigger condition may then be recorded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.