Method and system for inspection optimization in design and production of integrated circuits
US7665048B2 · kind B2 · utility
3Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2006 |
| Grant date | Feb 16, 2010 |
| Priority date | — |
| Expiry date | Nov 4, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for inspection optimization is provided. Inspection optimization improves the parametric and functional yield using optimized inspection lists for in-line semiconductor manufacturing metrology and inspection equipment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.