Method for making a vertical MOS transistor with embedded gate
US7666733B2 · kind B2 · utility
13Cited by
6References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 4, 2007 |
| Grant date | Feb 23, 2010 |
| Priority date | — |
| Expiry date | Mar 18, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/666
Abstract
According to the invention, a transistor of vertical MOS type is produced in which an insulating assembly (28) formed above the drain (26) comprises insulating zones (42, 44) either side of the drain; cavities extend under the insulating assembly, either side of the channel (69); the gate (77a, 77b) is formed either side of this insulating assembly; and portions of the gate are located inside the cavities. The invention applies to microelectronics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.