Process of manufacturing semiconductor device
US7666747B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2006 |
| Grant date | Feb 23, 2010 |
| Priority date | — |
| Expiry date | Nov 24, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method that suppresses etching damage without increasing a chip area of a semiconductor device. An integrated circuit including a MOS transistor is formed in a device area, and a discharge diffusion region is formed in a device area, and a discharge diffusion region is formed in a grid area. The discharge diffusion region is connected to a metal wiring of the integrated circuit via a contact hole. Therefore, when the metal wiring is formed by a dry etching method, an electric charge stored in the metal wiring is discharged to a semiconductor substrate through the discharge diffusion region. Thus, etching damage of the MOS transistor is reduced. Since the discharge diffusion region and the contact hole are formed within the grid area, they are cut off by a dicing process, thus causing no increase in chip area of the semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.