Split-gate memory cells and fabrication methods thereof
US7667261B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2007 |
| Grant date | Feb 23, 2010 |
| Priority date | — |
| Expiry date | Apr 17, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/30
Abstract
Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A top level of the active regions is lower than a top level of the isolation regions. A pair of floating gates is disposed on the active regions and aligned with the isolation regions, wherein a passivation layer is disposed on the floating gate to prevent thinning from CMP. A pair of control gates is self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates is disposed on the outer sidewalls of the pair of control gates along the second direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.