Using oxynitride spacer to reduce parasitic capacitance in CMOS devices

US7667275B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Yuanning Chen · Orlando, US
• Haowen Bu · Plano, US
• Kaiping Liu · Plano, US

Key dates

• Filing date: Sep 11, 2004
• Grant date: Feb 23, 2010
• Expiry date: Feb 24, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

A complementary metal oxide semiconductor (CMOS) device has a substrate 100, a gate structure 108 disposed atop the substrate, and spacers 250, deposited on opposite sides of the gate structure 108 to govern formation of deep source drain regions S, D in the substrate. Spacers 250 are formed of an oxynitride (SiOxNyCz) wherein x and y are non-zero but z may be zero or greater; such oxynitride spacers reduce parasitic capacitance, thus improving device performance. A method of fabricating a portion of a complementary metal oxide semiconductor (CMOS) device involves providing a substrate 100, forming a gate structure 108 over the substrate, depositing a first layer 104 atop the substrate on opposite sides of the gate structure to govern formation of deep source drain regions in the substrate, depositing an oxynitride (SiOxNyCz) layer 250 atop the first layer (in which x and y are non-zero but z may be zero or greater), depositing a second layer 112 atop the oxynitride layer, and depositing a nitride layer 114B atop the second layer.