Yuanning Chen
17Patents
4h-index
23Co-inventors
60Inventor score
Filing activity: Dec 17, 1999 → Mar 14, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6551946B1 | TWO-STEP OXIDATION PROCESS FOR OXIDIZING A SILICON SUBSTRATE WHEREIN THE FIRST STEP IS CARRIED OUT AT A TEMPERATURE BELOW THE VISCOELASTIC TEMPERATURE OF SILICON DIOXIDE AND THE SECOND STEP IS CARRIED OUT AT A TEMPERATURE ABOVE THE VISCOELASTIC TEMPERATURE | Electricity | 11 | Expired |
| US6541394B1 | Method of making a graded grown, high quality oxide layer for a semiconductor device | Electricity | 8 | Expired |
| US8552470B2 | Self-powered integrated circuit with multi-junction photovoltaic cell | Emerging Cross-Sectional Technologies | 6 | Active |
| US6303397A | Method for benchmarking thin film measurement tools | Emerging Cross-Sectional Technologies | 6 | Expired |
| US6930006B2 | Electronic circuit structure with improved dielectric properties | Electricity | 3 | Expired |
| US7704883B2 | Annealing to improve edge roughness in semiconductor technology | Electricity | 3 | Active |
| US6492712B1 | High quality oxide for use in integrated circuits | Electricity | 2 | Expired |
| US7033897B2 | Encapsulated spacer with low dielectric constant material to reduce the parasitic capacitance between gate and drain in CMOS technology | Electricity | 2 | Expired |
| US9048151B2 | Self-powered integrated circuit with photovoltaic cell | Emerging Cross-Sectional Technologies | 2 | Active |
| US7148153B2 | Process for oxide fabrication using oxidation steps below and above a threshold temperature | Electricity | 2 | Expired |
| US7569464B2 | Method for manufacturing a semiconductor device having improved across chip implant uniformity | Electricity | 1 | Active |
| US8883541B2 | Self-powered integrated circuit with multi-junction photovoltaic cell | Emerging Cross-Sectional Technologies | 1 | Active |
| US7276408B2 | Reduction of dopant loss in a gate structure | Electricity | 1 | Expired |
| US7800226B2 | Integrated circuit with metal silicide regions | Electricity | 0 | Active |
| US7667275B2 | Using oxynitride spacer to reduce parasitic capacitance in CMOS devices | Electricity | 0 | Active |
| US11004612B2 | Low temperature sub-nanometer periodic stack dielectrics | Electricity | 0 | Active |
| US7250356B2 | Method for forming metal silicide regions in an integrated circuit | Electricity | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.