Semiconductor device
US7667307B2 · kind B2 · utility
2Cited by
3References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2008 |
| Grant date | Feb 23, 2010 |
| Priority date | — |
| Expiry date | Mar 27, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
To actualize a reduction in the on-resistance of a small surface mounted package having a power MOSFET sealed therein. A silicon chip is mounted on a die pad portion integrated with leads configuring a drain lead. The silicon chip has, on the main surface thereof, a source pad and a gate pad. The backside of the silicon chip configures a drain of a power MOSFET and bonded to the upper surface of a die pad portion via an Ag paste. A lead configuring a source lead is electrically coupled to the source pad via an Al ribbon, while a lead configuring a gate lead is electrically coupled to the gate pad via an Au wire.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.