Interposer chip, method of manufacturing the interposer chip, and multi-chip package having the interposer chip
US7667331B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jul 8, 2008 |
| Grant date | Feb 23, 2010 |
| Priority date | — |
| Expiry date | Aug 4, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49155
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An interposer chip in accordance includes an insulating layer, conductive patterns and a dummy pattern. The conductive patterns are formed on the insulating layer. The dummy pattern is formed on the insulating layer to suppress a bending of the insulating layer. Further, the dummy pattern can have first isolating grooves formed along peripherals of the conductive patterns to isolate the dummy pattern from the conductive patterns. Thus, the interposer chip is not vulnerable to being bent. Further, an electrical short between the conductive patterns through the dummy pattern caused by particles is substantially avoided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.