Patent · US Active

Input buffer

US7667492B2 · kind B2 · utility

0Cited by

6References

13Claims

0Family size

Assignee

Freeescale Semiconductor, Inc. · US

Inventors

Kiyoshi Kase · Austin, US
May Len · Cedar Park, US
Dzung T. Tran · Austin, US

Key dates

Filing date	Dec 21, 2007
Grant date	Feb 23, 2010
Priority date	—
Expiry date	Dec 21, 2027

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/018521
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Methods and corresponding systems for buffering an input signal include outputting a first logic value in response to the input signal being below a lower threshold. A second logic value is output in response to the input signal rising above the lower threshold. Thereafter, the second logic value is maintained until the input exceeds a higher threshold and thereafter falls below the higher threshold. In response to the input signal falling below the higher threshold, the first logic value is output, and maintained at the first logic value, until the input falls below the lower threshold and thereafter rises above the lower threshold.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.