Optimizing data bandwidth across a variable asynchronous clock domain
US7669028B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2006 |
| Grant date | Feb 23, 2010 |
| Priority date | — |
| Expiry date | Jun 25, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1689
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention optimize data bandwidth across an asynchronous buffer in a system with a variable clock domain. A move signal may be asserted to transfer data associated with a command into the asynchronous buffer. After the data has been moved into the buffer, an acknowledge signal may indicate that the transfer is complete. A launch signal may transfer the data in the asynchronous buffer to memory. Embodiments of the present invention allow the processing of a next command to begin at the earliest possible time while data associated with a previous command is being transferred into and out of the buffer, thereby increasing throughput and improving performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.