Methodology to improve turnaround for integrated circuit design using geometrical hierarchy
US7669175B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 2007 |
| Grant date | Feb 23, 2010 |
| Priority date | — |
| Expiry date | Nov 6, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of designing a layout for manufacturing an integrated circuit is provided, in which computationally intensive portions of the design process, such as simulation of an image transferred through a mask design, or simulation of electrical characteristics of a circuit, are performed more efficiently by only performing such computations on single instance of computational subunits that have an identical geometrical context. Thus, rather than performing such computations based on the functional layout, for which typical design process steps result in significant flattening of the functional hierarchy, and therefore increase the cost of computation, the invention performs simulations on computational subunits stored in a hierarchy based on geometrical context, which minimizes the cost of simulation. The resulting simulation results are subsequently assembled according to the functional layout.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.