Coreless cavity substrates for chip packaging and their fabrication
US7669320B2 · kind B2 · utility
43Cited by
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36Claims
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Key dates
| Filing date | Apr 19, 2007 |
| Grant date | Mar 2, 2010 |
| Priority date | — |
| Expiry date | Mar 20, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49156
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method for fabricating an IC support for supporting a first IC die connected in series with a second IC die; the IC support comprising a stack of alternating layers of copper features and vias in insulating surround, the first IC die being bondable onto the IC support, and the second IC die being bondable within a cavity inside the IC support, wherein the cavity is formed by etching away a copper base and selectively etching away built up copper.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.