Patent · US Active

Structure and method for fabrication JFET in CMOS

US7670889B2 · kind B2 · utility

7Cited by
3References
19Claims
0Family size

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Inventors

Key dates

Filing dateJun 4, 2008
Grant dateMar 2, 2010
Priority date
Expiry dateJun 4, 2028

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D30/0512

Abstract

A design structure, and more particularly, to a design structure for manufacturing a JFET in SOI, a JFET and methods of manufacturing the JFET are provided. The JFET includes a gate poly formed directly on an SOI layer and a gate oxide layer interposed between outer edges of the gate poly and the SOI layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.