Patent · US Active

Single-wafer process for fabricating a nonvolatile charge trap memory device

US7670963B2 · kind B2 · utility

34Cited by

7References

8Claims

0Family size

Assignee

Cypress Semiconductor Corporation · US

Inventors

Krishnaswamy Ramkumar · San Jose, US
Sagy Levy · Jerusalem, IL

Key dates

Filing date	Sep 26, 2007
Grant date	Mar 2, 2010
Priority date	—
Expiry date	Sep 26, 2027

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY10S438/954
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method for fabricating a nonvolatile charge trap memory device is described. The method includes first forming a tunnel dielectric layer on a substrate in a first process chamber of a single-wafer cluster tool. A charge-trapping layer is then formed on the tunnel dielectric layer in a second process chamber of the single-wafer cluster tool. A top dielectric layer is then formed on the charge-trapping layer in the second or in a third process chamber of the single-wafer cluster tool.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.