Non-volatile memory in CMOS logic process
US7671401B2 · kind B2 · utility
23Cited by
15References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 28, 2005 |
| Grant date | Mar 2, 2010 |
| Priority date | — |
| Expiry date | Jul 8, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, apparatus, and system in which an embedded memory fabricated in accordance with a conventional logic process includes one or more electrically-alterable non-volatile memory cells, each having a programming transistor, a read transistor and a control capacitor, which share a common floating gate electrode. The under-diffusion of the source/drain regions of the programming transistor and control capacitor are maximized. In one embodiment, the source/drain regions of the programming transistor are electrically shored by transistor punch-through (or direct contact).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.