Empty vias for electromigration during electronic-fuse re-programming
US7671444B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2007 |
| Grant date | Mar 2, 2010 |
| Priority date | — |
| Expiry date | Jul 9, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The disclosure relates generally to integrated circuit (IC) chip fabrication, and more particularly, to an e-fuse device including an opening, a first via and a second via in an interlayer dielectric, wherein the opening, the first via and the second via are connected to an interconnect below the interlayer dielectric; a dielectric layer that encloses the first via and the second via; and a metal layer over the dielectric layer, wherein the metal layer fills the opening with a metal, and wherein the first via and the second via are substantially empty to allow for electromigration of the interconnect during re-programming of the e-fuse device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.