Semiconductor package having double layer leadframe
US7671451B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2005 |
| Grant date | Mar 2, 2010 |
| Priority date | — |
| Expiry date | May 30, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18301
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A leadframe chip scale package includes a double leadframe assembly. The first leadframe has a central die paddle and peripheral leads, and the second leadframe, superimposed over the first leadframe in the package, has peripheral leads. The peripheral leads of both leadframes are situated in at least one row along an edge of the package, and in some embodiments in a row along each of the four edges of the package. The leads are patterned such that when the second leadframe is superimposed over the first leadframe, the leads do not contact each other; in a plan view, the leads of the first leadframe appear to be interdigitated with the leads of the second leadframe.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.